SoC Physical Design -- Bangalore -- Well established 3years Old Company (Undertake Turnkey Projects) -- 3yrs to 9yrs -- Compensation Rs.9 lacs to Rs.26Lacs per annum

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Location     : Bangalore

Position      : Engineers / Senior Engineer

Role and Responsibilities

• Implementation of multimillion gate SoC designs in cutting edge process technologies (65nm, 40nm and 28nm)
• Work on all aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout
• Clear understanding and command over all aspects of physical design and ultra deep submicron technologies
• Experience in ASIC tapeouts, preferably in 65nm and below technology nodes
• Expertise in Synopsys, Magma or Cadence physical design tools
• Skill and experience in scripting using Tcl or Perl is highly desirable

Requirements: B.Tech / M. Tech in Electrical and Eclectronics / Electronics and Communication with a minimum of  3 years to 9 years experience in the relevant area

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